|Description||1024 X 1024 Channels Selectable Rate (2, 4, 8 Mbps) Non-blocking TDM Switch|
|Datasheet||Download ZL50017 datasheet
1024 channel x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch or 16.384 Mbps 16 serial TDM input, 16 serial TDM output streams Output streams can be configured as bidirectional for connection to backplanes Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Per-stream input bit delay with flexible sampling point selection Per-stream output bit and fractional bit advancement Per-channel constant or variable throughput delay for frame integrity and low latency applications Per-channel high impedance output control Per-channel message mode Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses:61 ns, 122 ns, 244 ns Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Ordering Information ZL50017GAC 256-ball PBGA ZL50017QCC 256-lead LQFP to +85 °C Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltageApplications
PBX and IP-PBX Small and medium digital switching platforms Remote access servers and concentrators Wireless base stations and controllers Multi service access platforms Digital Loop Carriers Computer Telephony Integration
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
The is a maximum x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has sixteen input streams - 15) and sixteen output streams - 15). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. All of the input and output streams operate at the same data rate and can be programmed at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The output streams can be configured to operate in bi-directional mode, in which case - 15 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are three modes of operation - Connection Mode, Message Mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In high impedance mode the selected output channel can be put into a high impedance state. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
1.0 Pinout Diagrams. 6 1.1 BGA Pinout. 6 1.2 QFP Pinout. 7 2.0 Pin Description. 8 3.0 Device Overview. 13 4.0 Data Rates and Timing. 14 4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. 14 4.2 ST-BUS and GCI-Bus Timing. 16 5.0 Data Input Delay and Data Output Advancement. 16 5.1 Input Bit Delay Programming. 17 5.2 Input Bit Sampling Point Programming. 18 5.3 Output Advancement Programming. 19 5.4 Fractional Output Bit Advancement Programming. 20 6.0 Data Delay Through the Switching Paths. 21 6.1 Variable Delay Mode. 21 6.2 Constant Delay Mode. 22 7.0 Connection Memory Description. 22 8.0 Connection Memory Block Programming. 23 8.1 Memory Block Programming Procedure. 23 9.0 Microprocessor Port. 23 10.0 Device Reset and Initialization. 24 10.1 Power-up Sequence. 24 10.2 Device Initialization on Reset. 24 10.3 Software Reset. 24 11.0 JTAG Port. 24 11.1 Test Access Port (TAP). 24 11.2 Instruction Register. 25 11.3 Test Data Registers. 25 11.4 BSDL. 25 12.0 Register Address Mapping. 26 13.0 Detailed Register Description. 27 14.0 Memory. 33 14.1 Memory Address Mappings. 33 14.2 Connection Memory Low (CM_L) Bit Assignment. 15.0 DC Parameters. 16.0 AC Parameters. 37
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