|Description||Enhanced 2 K Channel TDM Switch With Rate Conversion|
|Datasheet||Download ZL50020 datasheet
2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running 4.096, 8.192 and 16.384 Mbps 32 serial TDM input, 32 serial TDM output streams Output streams can be configured as bidirectional for connection to backplanes Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Per-stream input and output data rate conversion selection or 16.384 Mbps. Input and output data rates can differ Per-stream high impedance control outputs (STOHZ) for 16 output streams Per-stream input bit delay with flexible sampling point selection Ordering Information ZL50020GAC 256-ball PBGA ZL50020QCC 256-lead LQFP +85 °C Per-stream output bit and fractional bit advancement Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation Four frame pulse and four reference clock outputs Three programmable delayed frame pulse outputs Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses:61 ns, 122 ns, 244 ns Per-channel constant or variable throughput delay for frame integrity and low latency applications
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151 Per-channel high impedance output control Per-channel message mode Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltageApplications
PBX and IP-PBX Small and medium digital switching platforms Remote access servers and concentrators Wireless base stations and controllers Multi service access platforms Digital Loop Carriers Computer Telephony IntegrationDescription
The is a maximum x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams - 31) and thirty-two output streams - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50020 provides up to sixteen high impedance control outputs 15) to support the use of external tristate drivers for the first sixteen output streams - 15). The output streams can be configured to operate in bi-directional mode, in which case - 31 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
1.0 Pinout Diagrams. 6 1.1 BGA Pinout. 6 1.2 QFP Pinout. 7 2.0 Pin Description. 8 3.0 Device Overview. 14 4.0 Data Rates and Timing. 14 4.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing. 15 5.0 ST-BUS and GCI-Bus Timing. 18 6.0 Output Timing Generation. 18 7.0 Data Input Delay and Data Output Advancement. 21 7.1 Input Bit Delay Programming. 21 7.2 Input Bit Sampling Point Programming. 22 7.3 Output Advancement Programming. 24 7.4 Fractional Output Bit Advancement Programming. 25 7.5 External High Impedance Control Advancement. 26 8.0 Data Delay Through the Switching Paths. 26 8.1 Variable Delay Mode. 26 8.2 Constant Delay Mode. 27 9.0 Connection Memory Description. 28 10.0 Connection Memory Block Programming. 29 10.1 Memory Block Programming Procedure. 29 11.0 Device Performance Divided Clock and Multiplied Clock Modes. 29 11.1 Divided Clock Mode Performance. 30 11.2 Multiplied Clock Mode Performance. 30 12.0 Microprocessor Port. 30 13.0 Device Reset and Initialization. 30 13.1 Power-up Sequence. 31 13.2 Device Initialization on Reset. 31 13.3 Software Reset. 31 14.0 Pseudo Random Bit Generation and Error Detection. 31 15.0 PCM A-law/m-law Translation. 32 16.0 Quadrant Frame Programming. 33 17.0 JTAG Port. 33 17.1 Test Access Port (TAP). 33 17.2 Instruction Register. 34 17.3 Test Data Registers. 34 17.4 BSDL. 34 18.0 Register Address Mapping. 35 19.0 Detailed Register Description. 36 20.0 Memory. 54 20.1 Memory Address Mappings. 54 20.2 Connection Memory Low (CM_L) Bit Assignment. 54 20.3 Connection Memory High (CM_H) Bit Assignment. 21.0 DC Parameters. 22.0 AC Parameters. 59
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