Details, datasheet, quote on part number: ZL50021
PartZL50021
Category
DescriptionEnhanced 4 K Channel TDM Switch With Stratum 3 DPLL
CompanyZarlink Semiconductor
DatasheetDownload ZL50021 datasheet
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Features, Applications
ZL50021 Enhanced 4 K Digital Switch with Stratum 3 DPLL

x 4096-channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384 Mbps or using a combination of ports running 4.096, 8.192 and/or 16.384 Mbps 32 serial TDM input, 32 serial TDM output streams Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 3 specifications Output clocks have less than ns of jitter (except for the 1.544 MHz output) DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs Ordering Information ZL50021GAC 256-ball PBGA ZL50021QCC 256-lead LQFP +85 C Programmable key DPLL parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range) Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Output streams can be configured as bidirectional for connection to backplanes

Figure - ZL50021 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

Per-stream input and output data rate conversion selection or 16.384 Mbps. Input and output data rates can differ Per-stream high impedance control outputs (STOHZ) for to 16 output streams Per-stream input bit delay with flexible sampling point selection Per-stream output bit and fractional bit advancement Per-channel ITU-T G.711 PCM A-Law/-Law Translation Multiple frame pulse and reference clock outputs Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses: 61 ns, 122 ns, 244 ns Per-channel constant or variable throughput delay for frame integrity and low latency applications Per Stream Bit Error Rate Test circuits Per-channel high impedance output control Per-channel message mode Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage

Applications

PBX and IP-PBX Small and medium digital switching platforms Wireless base stations and controllers Remote access servers and concentrators Multi service access platforms Digital Loop Carriers Computer Telephony Integration

Description

The is a maximum x 4,096 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams - 31) and thirty-two output streams - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50021 provides up to sixteen high impedance control outputs 15) to support the use of external tristate drivers for the first sixteen output streams - 15). The output streams can be configured to operate in bi-directional mode, in which case - 31 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER Mode and High Impedance Mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz provided - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter attenuation. The jitter attenuation function exceeds the Stratum 3 specification. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.


 

Some Part number from the same manufacture Zarlink Semiconductor
ZL50022 Enhanced 4 K Channel TDM Switch With Stratum 4E DPLL
ZL50023 Enhanced 4 K Channel TDM Switch With Rate Conversion
ZL50030 Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface, 32 Bi-directional Backplane Streams And 16 Bi-directional Local Streams
ZL50050 8 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 32 Input And 32 Output ...
ZL50050GAC Description = ;; Package Type = Bga ;; No. Of Pins = 196
ZL50051 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (8 or 16 Mbps) And 64 Input And 64 Output Streams
ZL50052 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (32 Mbps) And 16 Input And 16 Output Streams
ZL50053 8 K Channel Digital Switch With High Jitter Tolerance, Single Rate (8 or 16 Mbps) And 64 Input And 64 Output Streams
ZL50057 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 48 Input And 48 Output ...
ZL50057GAC Description = ;; Package Type = Bga ;; No. Of Pins = 272
ZL50058 12 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 48 Input And 48 Output ...
ZL50058GAC Description = ;; Package Type = Bga ;; No. Of Pins = 272
ZL50060 16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 64 Input And 64 Output ...
ZL50060GAC Description = ;; Package Type = Bga ;; No. Of Pins =
ZL50061 16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16 or 32 Mbps), 64 Input And 64 Output ...
ZL50061GAC Description = ;; Package Type = Bga ;; No. Of Pins =
ZL50062 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate (2, 4, 8 or 16 Mbps) And 64 Input And 64 Outputs Streams
ZL50062GAC Description = ;; Package Type = Bga ;; No. Of Pins =
ZL50063 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate (32 Mbps) And 32 Input And 32 Output Streams
ZL50063GAC Description = ;; Package Type = Bga ;; No. Of Pins = 196
ZL50064 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate (2, 4, 8 or 16 Mbps) And 64 Input And 64 Output Streams
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