Details, datasheet, quote on part number: ZL50062
PartZL50062
Category
Description16 K Channel Digital Switch With High Jitter Tolerance, Single Rate (2, 4, 8 or 16 Mbps) And 64 Input And 64 Outputs Streams
CompanyZarlink Semiconductor
DatasheetDownload ZL50062 datasheet
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Features, Applications

16K-Channel Digital Switch with High Jitter Tolerance, Single Rate or 16Mbps), and 64 Inputs and 64 Outputs Data Sheet Features

x 16,384-channel non-blocking unidirectional switching.The Backplane and Local inputs and outputs can be combined to form a non-blocking switching matrix with 64 input streams and 64 output streams x 8,192-channel non-blocking Backplane input to Local output stream switch x 8,192-channel non-blocking Local input to Backplane output stream switch x 8,192-channel non-blocking Backplane input to Backplane output switch x 8,192-channel non-blocking Local input to Local output stream switch Backplane port accepts 32 input and 32 output ST-BUS streams with fixed data rates or 16.384Mbps Local port accepts 32 input and 32 output STBUS streams with fixed data rates or 16.384Mbps Exceptional input clock jitter tolerance (17ns) Ordering Information ZL50064QCC 256-Ball PBGA 256-Pin LQFP

+85° C Per-stream bit delay for Local and Backplane input streams Per-stream advancement for Local and Backplane output streams Constant 2-frame throughput delay for frame integrity Per-channel high impedance output control for Local and Backplane streams Per-channel driven-high output control for Local and Backplane streams Per-channel message mode for Local and Backplane output streams Connection memory block programming for fast device initialization


Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.

Automatic selection between ST-BUS and GCI-Bus operation Non-multiplexed Motorola microprocessor interface Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard Memory Built-In-Self-Test (BIST), controlled via microprocessor register 1.8V core supply voltage 3.3V I/O supply voltage 5V tolerant inputs, outputs and I/Os

Applications

Central Office Switches (Class 5) Media Gateways Class-independent switches Access Concentrators Scalable TDM-Based Architectures Digital Loop Carriers

The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four different data rates, or 16.384Mbps. All 64 input and 64 output streams must operate at the same data rate. The ZL50062/4 contains two data memory blocks (Backplane and Local) to provide the following switching path configurations: Input-to-Output Unidirectional, supporting x 16K switching Backplane-to-Local Bi-directional, supporting x 8K data switching, Local-to-Backplane Bi-directional, supporting x 8K data switching, Backplane-to-Backplane Bi-directional, supporting x 8K data switching. Local-to-Local Bi-directional, supporting x 8K data switching.

The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (stored in data memory) to be switched. In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output streams on a per channel basis. This feature is useful for transferring control and status information to external circuits or other ST-BUS devices. The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCIBus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the establishment of full switch functionality. During this period, the input frame pulse format is determined before switching begins. The device provides FP16o, C8o and C16o outputs to support external devices connected to the outputs of the Backplane and Local ports. A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and switching configurations. The microprocessor port provides access for Register read/write, Connection Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control signals. The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The ZL50062 and ZL50064 are each available in one package: x 17mm body, 1mm ball-pitch, x 28mm body, 0.40mm pin-pitch, 256-LQFP.


 

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