|Category||Communication => Network => Ethernet/DS1/E1 (T1/E1)|
|Description||1024 Channel (32 T1/E1) Circuit Emulation Services over Packet Processor
The ZL50111 is a highly functional TDM to Packet bridging device that provides structured and unstructured circuit emulation services (CES) for T1/E1 streams across a packet network based on Ethernet technology. The ZL50111 is capable of assembling user-defined packets of TDM traffic from the TDM access interface and transmitting them from the Ethernet interfaces using a variety of protocols such as Ethernet VLAN's, IP (both versions 4 and 6) and MPLS. The device also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. The circuit emulation features in the ZL50111 comply with the relevant standards currently being developed within the IETF's PWE3 working group. The ZL50111 incorporates a range of powerful clock recovery mechanisms and sufficient on-chip memory that external memory is not required in most applications. This reduces system costs and simplifies the design.
1024 bi-directional 64 kbps channels in structured, synchronous CES
32 T1/E1 or 2 T3/E3 unstructured, asynchronous CES, with integral per stream clock recovery
Interface either directly to LIU, via a framer, or via a TDM backplane
Dual reference Stratum 3, 4 and 4E PLL for synchronous operation
3 x 100 Mbps MII or Dual Redundant 1000 Mbps GMII/PCS(TBI) Ethernet Interfaces
Flexible 32 bit host CPU interface (Motorola PowerQUICC II compatible)
On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
Flexible, multi-protocol packet encapsulation
Packet sequencing to allow lost packet detection
Four classes of service with programmable priority mechanisms (WFQ and SP)
Classification of incoming packets at layers 2, 3, 4, and 5
Leased Line support over packet network
Multi-Tenant Unit access concentration
Packet switched backplane applications
TDM backplane extension / expansion
|Datasheet||Download ZL50111 datasheet
General Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network Grooming capability for Nx64 Kbps trunking Ordering Information ZL50114GAG 552 PBGA 552 PBGA 552 PBGA
to +85°C Network Interfaces x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Interfaces
Circuit Emulation Services Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards for CESoPSN and SAToP Complies with CES draft IAs for MEF and MFA Structured, synchronous CES Unstructured, asynchronous CES, with integral per stream clock recovery
System Interfaces Flexible 32 bit host CPU interface (Motorola PowerQUICCTM compatible) On-chip packet memory for self-contained operation, with buffer depths of over to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms
TDM Interfaces 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes to 1024 bi-directional 64 Kbps channels Direct connection to LIUs, framers, backplanes Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation
Packet Processing Functions Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413., IETF CESoPSN, IETF SAToP and user programmable Packet re-sequencing to allow lost packet detectionPW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others
(Jitter Buffer Compensation for ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface External Memory Interface (optional)
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.Triple 100 Mbps MII Fast Ethernet or Dual Redudnat 1000 Mbps GMII/ TBI Gigabit Ethernet
Flexible classification of incoming packets at layers 3, 4, and 5 Supports to 128 separate CES connections across the Packet Switched NetworkFour classes of service with programmable priority mechanisms (WFQ and SP) using egress queues
Circuit Emulation Services over Packet Networks Leased Line support over packet networks Multi-Tenant Unit access concentration TDM over Cable Fibre To The Premises G/E-PON Layer 2 VPN servicesCustomer-premise and Provider Edge Routers and Switches Packet switched backplane applications
The ZL50110/11/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The ZL50110/11/14 provides both structured and unstructured circuit emulation services (CES) for 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also supports unstructured T3, E3 and STS-1 streams. The circuit emulation features in the ZL50110/11/14 family comply with the ITU Recommendation Y.1413, as well as the emerging CES standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance (MFA). The ZL50110/11/14 also complies with the standards currently being developed within the IETF's PWE3 working group, listed below. Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) - draft-ietfpwe3-cesopsn
The ZL50110/11/14 provides either triple 100 Mbps MII ports or dual redundanct 1000 Mbps GMII/TBI ports. The ZL50110/11/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL50110/11/14. The ZL50110/11/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. The ZL50110/11/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/14 supports a range of different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used to help minimize latency variation in the TDM data. Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface. Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to maintain timing integrity. The ZL50110/11/14 family includes sufficient on-chip memory that external memory is not required in most applications. This reduces system costs and simplifies the design. For applications that do require more memory (e.g., high stream count or high latency), the device supports to 8 Mbytes of SSRAM. A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC.
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