Details, datasheet, quote on part number: ZL50118GAG
PartZL50118GAG
CategoryCommunication => Network => Network Processors
Description128 Channel CESoP Processor with dual Ethernet interface

The ZL50120 CESoP processor is a highly functional TDM to Packet bridging device providing both structured and unstructured circuit emulation services (CES) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The ZL50120 also supports unstructured J2, T3, E3 and STS-1. The device incorporates a range of powerful clock recovery mechanisms for each TDM stream and a dual Ethernet interface to aggregate data traffic with voice traffic.

Features
Circuit Emulation Services over Packet (CESoP)transport for MPLS, IP and Ethernet networks
On-chip timing & synchronization recovery across a packet network
On-chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors
TDM Interface provides 128 bi-directional 64 Kbps channels or 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
Compatible with H.110, H-MVIP, ST-BUS backplane
Direct connection to LIUs, framers, backplanes
100 Mbps MII interface for user data traffic
100 Mbps MII FE or 1000 Mbps GMII/TBI interface for network uplink
Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable
Complies with ITU-T recommendation Y.1413, IETF PWE3 draft standards CESoPSN and SAToP and CES draft IAs from MEF and MFA
On-chip packet memory with 128 ms jitter buffer
Typical Applications
TDM traffic over packet networks
Leased Line support over packet networks
3G Wireless Backhaul
TDM over Cable
TDM over WiFi (802.11x)
TDM over WiMAX (802.16)
FTTx (Fibre To The Premises)
G/E PON (Passive Optical Networks)
Layer 2 VPN services
Customer-premise and Provider Edge Routers and Switches
Ethernet and IP based IADs
IP DSLAM, NG-DLC
MDU/MTU
CompanyZarlink Semiconductor
DatasheetDownload ZL50118GAG datasheet
Quote
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Packages324 Ball PBGA
  

 

Features, Applications

General Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network On chip dual reference Stratum 3 DPLL Grooming capability for Nx64 Kbps trunking Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors

Ordering Information ZL50120GAG 324 Ball PBGA 324 Ball PBGA 324 Ball PBGA

° C Customer Side TDM Interfaces 1 STS-1 ports H.110, H-MVIP, ST-BUS backplane to 128 bi-directional 64 Kbps channels Direct connection to LIUs, framers, backplanes

Circuit Emulation Services Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards CESoPSN and SAToP Complies with CES draft IAs from MEF and MFA Structured, synchronous CES Unstructured, asynchronous CES with integral per-stream clock recovery

Customer Side or Provider Side Packet Interfaces 100 Mbps MII Fast Ethernet
Provider Side Packet Interfaces 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet
PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others

(Jitter Buffer Compensation for ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.

100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet
System Interfaces Flexible 32 bit Motorola host interface
On-chip packet memory with jitter buffer compensation for over ms of packet delay variation

Packet Processing Functions Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable Packet re-sequencing to allow lost packet detection and re-ordering Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues Programmable classification of incoming packets at layers 2 through 5 Wire speed processing of all packets regardless of classification providing low latency Supports to 128 separate CES connections across the Packet Switched Network

Applications

Circuit Emulation Services over Packet Networks Leased Line support over packet networks TDM over Cable TDM over WiFi (802.11x) TDM over WiMAX (802.16) Fibre To The Premises G/E-PON Layer 2 VPN services

Customer-premise and Provider Edge Routers and Switches Ethernet and IP based IADs

1.0 Physical Specification. 9 2.0 External Interface Description. 23 2.1 TDM Interface. 23 2.1.1 TDM stream connections. 23 2.1.2 TDM Signals common 25 2.2 PAC Interface. 26 2.3 Packet Interfaces. 27 2.4 CPU Interface. 32 2.5 System Function Interface. 35 2.6 Test Facilities. 35 2.6.1 Administration, Control and Test Interface. 35 2.6.2 JTAG Interface. 36 2.7 Miscellaneous Inputs. 36 2.8 Power and Ground Connections. 37 2.9 Internal Connections. 2.10 No Connections. 38 2.11 Device ID. 38 3.0 Typical Applications. 39 3.1 Leased Line Provision. 39 3.2 Remote Concentrator Unit. 40 3.3 FTTP. 41 3.4 Wireless - WiFi or WiMAX. 42 3.5 Digital Loop Carrier. 43 3.6 Integrated Access Device. 44 4.0 Functional Description. 44 4.1 Block Diagram. 45 4.2 Data and Control Flows. 45 4.3 TDM Interface. 46 4.3.1 TDM Interface Block. 46 4.3.2 Structured TDM Port Data Formats. 47 4.3.3 TDM Clock Structure. 48 4.3.3.1 Synchronous TDM Clock Generation. 48 4.3.3.2 Asynchronous TDM Clock Generation. 48 4.4 Payload Assembly. 48 4.4.1 Structured Payload Operation. 49 4.4.1.1 Payload Order. 50 4.4.2 Unstructured Payload Operation. 50 4.5 Protocol Engine. 51 4.6 Packet Transmission. 51 4.7 Packet Reception. 51 4.8 TDM Formatter. 51 4.9 Ethernet Traffic Aggregation. 51 5.0 Clock Recovery. 52 5.1 Differential Clock Recovery. 52 5.2 Adaptive Clock Recovery. 53 6.0 System Features. 54 6.1 Latency. 54 6.2 Loopback Modes. 54 6.3 Host Packet Generation. 54 6.4 Loss of Service (LOS). 55 6.5 Power Up sequence. 55


 

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