Details, datasheet, quote on part number: ZL50119GAG
PartZL50119GAG
CategoryCommunication => Network => Network Processors
Description64 Channel (2 T1/E1) CESoP Processor With Dual Ethernet Interface
The ZL50119 CESoP processor is a highly functional TDM to Packet bridging device providing both structured and unstructured circuit emulation services (CES) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The device incorporates a range of powerful clock recovery mechanisms for each TDM stream and a dual Ethernet interface to aggregate data traffic with voice traffic.
CompanyZarlink Semiconductor
DatasheetDownload ZL50119GAG datasheet
Quote
Find where to buy
 
PackagesPBGA
  

 

Features, Applications

General Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network On chip dual reference Stratum 3 DPLL Grooming capability for Nx64 Kbps trunking Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors

ZL50115GAG 324 Ball PBGA trays, bake ZL50116GAG 324 Ball PBGA trays, bake ZL50117GAG 324 Ball PBGA trays, bake ZL50118GAG 324 Ball PBGA trays, bake ZL50119GAG 324 Ball PBGA trays, bake ZL50120GAG 324 Ball PBGA trays, bake ZL50115GAG2 324 Ball PBGA** trays, bake ZL50116GAG2 324 Ball PBGA** trays, bake ZL50117GAG2 324 Ball PBGA** trays, bake ZL50118GAG2 324 Ball PBGA** trays, bake ZL50119GAG2 324 Ball PBGA** trays, bake ZL50120GAG2 324 Ball PBGA** trays, bake **Pb Free Tin/Silver/Copper dry pack

Circuit Emulation Services Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards CESoPSN and SAToP Complies with CESoP Implementation Agreements from MEF 8 and MFA 8.0.0 Structured, synchronous CESoP with clock recovery Unstructured, asynchronous CESoP with integral per-stream clock recovery

to 128 bi-directional 64 Kbps channels Direct connection to LIUs, framers, backplanes

Customer Side Packet Interfaces 100 Mbps MII Fast Ethernet (ZL50118/19/20 only) (may also be used as a second provider side packet interface) Provider Side Packet Interfaces 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet

Customer Side TDM Interfaces 1 STS-1 ports H.110, H-MVIP, ST-BUS backplane
PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others

(Jitter Buffer Compensation for ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.

100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet
System Interfaces Flexible 32 bit Motorola host interface
On-chip packet memory with jitter buffer compensation for over ms of packet delay variation

Packet Processing Functions Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable Packet re-sequencing to allow lost packet detection and re-ordering Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues Programmable classification of incoming packets at layers 2 through 5 Wire speed processing of all packets regardless of classification providing low latency Supports to 128 separate CESoP connections across the Packet Switched Network

Applications

Circuit Emulation Services over Packet Networks Leased Line support over packet networks TDM over Cable TDM over WiFi (802.11x) TDM over WiMAX (802.16) Fibre To The Premises G/E-PON Layer 2 VPN services

Customer-premise and Provider Edge Routers and Switches Ethernet and IP based IADs

The following table captures the changes from the July 2005 issue. Page 38, 39 Item Section 4.5 and Section 4.6.2 Change Added external pull-up/pull-down resistor recommendations for SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.

The following table captures the changes from the April 2005 issue. Page 49 Section 6.3 Item Change Added Section 6.3 SYSTEM_CLK Considerations.

The following table captures the changes from the January 2005 issue. Page Item Change Clarified data sheet to indicate ZL5011x supports clock recovery in both synchronous and asynchronous modes of operation. 84 Figure 42 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API.

The following table captures the changes from the November 2004 issue. Page 38 Section 4.6.1 Item Change Added 5 kohm pulldown recommendation to GPIO signals.


 

Related products with the same datasheet
ZL50119GAG2
Some Part number from the same manufacture Zarlink Semiconductor
ZL63039 12x6.25 Gb/s Multirate VCSEL DriverThe Zarlink ZL63039 VCSEL driver is a 12-channel, monolithic SiGe BiCMOS integrated circuit that provides all the functionally needed to digitally modulate commercially
ZL62089 2x6.25 Gb/s TIA/LA ReceiverThe Zarlink ZL62089 receiver is a patented twelve-channel, monolithic SiGe BiCMOS integrated circuit that combines high-sensitivity transimpedance amplifiers with high-gain
ZL62024 4x5 Gb/s TIA/LA ReceiverThe Zarlink ZL62024 receiver is a patented 4-channel, monolithic SiGe BiCMOS integrated circuit that combines high-sensitivity transimpedance amplifiers with high-gain limiting
ZL63034 4x6.25 Gb/s Multirate VCSEL DriverThe Zarlink ZL63034 VCSEL driver is a 4-channel, monolithic SiGe BiCMOS integrated circuit that provides all the functionally needed to digitally modulate commercially
MT90883 256 Channel TDM-to-Packet ProcessorThe MT90883 is highly functional TDM to Packet bridging device. It provides a bridge between a WAN environment based on constant bit rate TDM streams and a packet domain
ZL30130 OC-12/STM-4 SONET/SDH/GbE Stratum 2/3/3E System Synchronizer/SETSThe ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality
ZL30136 GbE And Telecom Rate Network Interface SynchronizerThe ZL30136 GbE and Telecom Rate Network Interface Synchronizer is a highly integrated cost-effective device that provides timing for network interface
ZL30138 OC-192/STM-64 SONET/SDH/10GbE Stratum 2/3/3E System Synchronizer/SETSThe ZL30138 SONET/SDH/Ethernet Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality
ZL40000 3/6 Channel DC To 2 GHz Power SplitterThe ZL40000 is an ultra high linearity RF power divider. The device provides a 75 Ohm Input impedance to a broad band RF input Signal. The signal is buffered through
ZL70250 Ultra Low Power RF TransceiverFull product information, including datasheet and user manual, is available for qualified customers. For more information contact Medical sales (http://ulp.zarlink.com/ulp_sales_contacts.htm).The
ZL30321 GbE/SONET/SDH/PDH Network Interface SynchronizerThe ZL30321 SONET/SDH/GbE Mulit-Rate Line Card Synchronizer is a highly integrated device that provides timing for network interface cards. It incorporates
ZL30131 OC-192/STM-64 SONET/SDH/10GbE Network Interface SynchronizerThe ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH
ZL30132 OC-192/STM-64 SONET/SDH/10GbE Network Interface SynchronizerThe ZL30132 OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer is a highly integrated device that provides timing for network interface
ZL30138 OC-192/STM-64 SONET/SDH/10GbE Stratum 2/3/3E System Synchronizer/SETSA full Data Sheet is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com.The ZL30138
ZL30130 OC-12/STM-4 SONET/SDH/GbE Stratum 2/3/3E System Synchronizer/SETSThe ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality
ISL22511 Single Push Button Controlled Potentiometer (XDCP??), Low Noise, Low Power, 32 Taps, PushButton Controlled PotentiometerThe Intersil ISL22511 is a three-terminal digitally-controlled potentiometer (XDCP)
ISL22512 Single Push Button Controlled Potentiometer (XDCP??), Low Noise, Low Power, 16 Taps, PushButton Controlled PotentiometerThe Intersil ISL22512 is a three-terminal digitally-controlled potentiometer (XDCP)
ISL3332 3.3V, 15kV ESD Protected, Two Port, Dual Protocol (RS-232/RS-485) TransceiversThe ISL333, ISL3333 are two port interface ICs where each port can be independently configured as a single RS-485/422 transceiver,
ISL3330 3.3V, 15kV ESD Protected, Dual Protocol (RS-232/RS-485) TransceiversThese devices are BiCMOS interface ICs that are user configured as either a single RS-422/RS-485 differential transceiver, or as a dual
ICM7244 8-Character, Microprocessor-Compatible, LED Display Decoder DriverThe ICM7244 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor
ISL54105 TMDS RegeneratorThe ISL54105 is a high-performance TMDS timing regenerator containing a programmable equalizer and a clock data recovery (CDR) function for each of the 3 TMDS pairs in an HDMI or DVI signal.
 
0-C     D-L     M-R     S-Z