|Category||Communication => Network => Switches|
|Description||Managed 5-Port Fast Ethernet Switch
The ZL50405 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 5 ports at 10/100 Mbps and a CPU interface for managed switch applications. The ZL50405 supports up to 4 K MAC addresses and port-based Virtual LANs (VLANs). It provides powerful QoS functions for various multimedia and mission-critical applications.
|Datasheet||Download ZL50405 datasheet
Integrated Single-Chip 10/100 Mbps Ethernet Switch Four 10/100 Mbps auto-negotiating Fast Ethernet (FE) ports with RMII, MII, GPSI, Reverse MII & Reverse GPSI interface options One 10/100 Mbps auto-negotiating port with MII interface option, that can be used as a WAN uplink a 9th port a 10/100 Mbps Fast Ethernet (FE) CPU port with Reverse MII interface option Embedded 2.0 Mbits (256 KBytes) internal memory for control databases and frame data buffer Supports jumbo frames to 4 KBytes CPU access supports the following interface options: 8/16-bit ISA interface Serial interface with MII port; recommended for light management Serial interface in lightly managed mode, or in unmanaged mode with optional I2C EEPROM interface Ethernet IEEE 802.3x flow control for full duplex ports, back pressure flow control for half duplex ports Ordering Information ZL50405GDG2 208-Ball LBGA 208-Ball LBGA**
**Pb Free Tin/Silver/Copper ° C Built-in reset logic triggered by system malfunction Built-In Self Test for internal SRAM IEEE-1149.1 (JTAG) test port
L2 switching MAC address self learning, 4 K MAC addresses MAC address table supports unicast and multicast MAC address and IP multicast address learning Supports IP Multicast with IGMP snooping, K IP Multicast groups
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Supports the following spanning standards IEEE 802.1D spanning tree IEEE 802.1w rapid spanning tree Supports Ethernet multicasting and broadcasting and flooding control
Supports the following VLAN standards port-based VLAN IEEE 802.1Q tag-based VLAN, 4 K VLANs Supports both shared VLAN learning (SVL) and independent VLAN learning (IVL) of MAC addresses Limited support for VLAN stacking ("Q-in-Q")
Search engine classification Classifies packets based on single field - Source and destination L4 logical ports, or - TOS/DS, or - VLAN (IEEE or - Physical port Assigns a transmission priority and drop precedence Packet filtering and security Static address filtering for source and/or destination MAC addresses Static MAC address not subject to aging Secure mode freezes MAC address learning (each port may independently use this mode) IEEE 802.1x access control Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of port VLAN ID
Two (2) transmission classes for FE ports and four (4) transmission classes for uplink port Scheduling using weighted fair queuing (WFQ) or strict priority (SP) discipline At egress, per-queue weighted random early discard (WRED) with 2 drop precedence levels Configurable WRED thresholds For FE ports, supports ingress and egress rate control Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) Granularity of rate regulation to 16 Kbps Ingress rate regulated using WRED, with 2 drop precedence levels, or flow control Output traffic regulation per class available on uplink port Fully supports Differentiated Services' Expedited and Assured Forwarding (EF and AF) per-hop behaviours Intelligent buffer management Achieves high buffer utilization while ensuring fairness among traffic classes and ports Buffer reservations per class and per source port Failover Features Rapid link failure detection using hardware-generated heartbeat packets link failover in less than 50 ms Supports concentration mode
Supports IEEE 802.3ad link aggregation Eight (8) groups to 4 ports per group Supports load sharing among trunk ports based on: - Source port - Source and/or destination MAC address Traffic Mirroring Physical port based (RMII enabled ports only) Source or destination MAC address based MAC address pair based Supports module hot swap on all portsDescription
The is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 4 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for managed, lightly managed and unmanaged switch applications. The chip supports 4 K MAC addresses and 4 K tagged-based Virtual LANs (VLANs). With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50405 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50405 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50405 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50405 supports to 8 groups of port trunking/load sharing. Each group can contain to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50405 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50405 is fabricated using 0.18 micron technology. The ZL50405 is packaged a 208-pin Ball Grid Array package.
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