|Category||Communication => Network => Ethernet/DS1/E1 (T1/E1) => Switches => Unmanaged Switches|
|Description||Description = Unmanaged 16-Port 10/100M Ethernet Switch ;; Package Type = Bga ;; No. Of Pins = 553|
|Datasheet||Download ZL50415 datasheet
Integrated Single-Chip 10/100 Mbps Ethernet Switch 16 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces. Serial CPU interface for configuration Supports one Frame Buffer Memory domain with SRAM at 100 MHz Supports SRAM domain memory size 1 MB, 2 MB Applies centralized shared memory architecture to 64K MAC addresses Maximum throughput is 1.6 Gbps non-blocking High performance packet forwarding (4.762M packets per second) at full wire speed Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoS-enabled ports Load sharing among trunked ports can be based Ordering Information ZL50415/GKC
85°C on source MAC and/or destination MAC. Port Mirroring to a dedicated mirroring port Full set of LED signals provided by a serial interface 2 port trunking groups with 4 10/100 ports per group Built-In Self Test for internal and external SRAM Traffic Classification
4 transmission priorities for Fast Ethernet ports with 2 dropping levels Classification based on: - Port based priority - VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines Provides 2 levels of dropping precedence with WRED mechanism User controls the WRED thresholds. Buffer management: per class and per port buffer reservations Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID.
Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction I2C EEPROM for configuration 553 BGA packageDescription
The is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, for unmanaged switch applications. The chip supports to 64K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate to 3.571M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. The Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously. With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the ZL50415 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50415 recognizes a total of 16 UDP/TCP logical ports, 8 hardwired and 8 programmable (including one programmable range). The ZL50415 supports 2 groups of port trunking/load sharing. Each 10/100 group can contain to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50415 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. The ZL50415 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50415 is packaged a 553-pin Ball Grid Array package.
1.0 Block Functionality. 9 1.1 Frame Data Buffer (FDB) Interfaces. 1.2 10/100 MAC Module (RMAC). 9 1.3 Configuration Interface Module. 9 1.4 Frame Engine. 9 1.5 Search Engine. 9 1.6 LED Interface. 9 1.7 Internal Memory. 9 2.0 System Configuration. 10 2.1 Configuration Mode. 2.2 I2C Interface. 10 2.2.1 Start Condition. 10 2.2.2 Address. 10 2.2.3 Data Direction. 10 2.2.4 Acknowledgment. 10 2.2.5 Data. 10 2.2.6 Stop Condition. 11 2.3 Synchronous Serial Interface. 11 2.3.1 Write Command. 11 2.3.2 Read Command. 3.0 ZL50415 Data Forwarding Protocol. 12 3.1 Unicast Data Frame Forwarding. 12 3.2 Multicast Data Frame Forwarding. 13 4.0 Memory Interface. 14 4.1 Overview. 14 4.2 Detailed Memory Information. 14 4.3 Memory Requirements. 14 5.0 Search Engine. 15 5.1 Search Engine Overview. 15 5.2 Basic Flow. 15 5.3 Search, Learning, and Aging. 15 5.3.1 MAC Search. 15 5.3.2 Learning. 16 5.3.3 Aging. 16 5.4 Quality of Service. 16 5.5 Priority Classification Rule. 17 5.6 Port Based VLAN. 17 5.7 Memory Configurations. 18 6.0 Frame Engine. 20 6.1 Data Forwarding Summary. 20 6.2 Frame Engine Details. 20 6.2.1 FCB Manager. 6.2.2 Rx Interface. 21 6.2.3 RxDMA. 21 6.2.4 TxQ Manager. 21 6.3 Port Control. 21 6.4 TxDMA. 21 7.0 Quality of Service and Flow Control. 21 7.1 Model. 21 7.2 Four QoS Configurations. 23 7.3 Delay Bound. 23
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