Details, datasheet, quote on part number: ZL50416GKG2
PartZL50416GKG2
CategoryCommunication => Network => Switches
DescriptionManaged 16-Port Fast Ethernet Switch
The ZL50416 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps, and a CPU interface for managed and unmanaged switch applications.
CompanyZarlink Semiconductor
DatasheetDownload ZL50416GKG2 datasheet
PackagesHSBGA
  

 

Features, Applications

Features

Sixteen 10/100 Mbps auto-negotiating Fast Ethernet (FE) ports with RMII or GPSI (7WS) interface options per port

Supports one Frame Data Buffer (FDB) memory domains or 2 MB) with pipelined, sync-burst SRAM at 100 MHz

**Pb Free Tin/Silver/Copper to 85C Packet Filtering and Port Security

Static address filtering for source and/or destination MAC Static MAC address not subject to aging Secure mode freezes MAC address learning, each port may independently use this mode

MAC address self learning, to 64K MAC addresses Supports port-based and tagged-based VLAN (IEEE 802.1Q) Supports to 255 VLANs and IP multicast groups VLAN tag insertion and stripping selectable on a per port, per VLAN basis Supports spanning tree on per-system (IEEE 802.1D/w) or per-VLAN basis (IEEE 802.1s)

Supports IP Multicast with IGMP snooping High performance packet classification and switching at full-wire speed CPU access supports the following interface options:

8/16-bit ISA interface in managed mode Serial interface in unmanaged mode, with optional I2C EEPROM support

Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control for best effort frames even on QoSenabled ports QoS Support

4 transmission priorities for Fast Ethernet ports Per-queue weighted random early discard (WRED) with 2 drop precedence levels Scheduling using delay bounded (DB), strict priority (SP), and Weighted Fair Queuing (WFQ) disciplines User controlled WRED thresholds

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

Buffer management: per-class, shared, and per-port buffer reservations

Port-based priority: priority in a frame can be overwritten by the priority of port VLAN Priority field in VLAN tagged frame (IEEE 802.1p) DS/TOS field in IP packet UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range

The drop precedence of the above classifications is programmable Supports IEEE 802.3ad link aggregation 2 port trunking groups

two groups for 10/100 ports, with to 4 ports per group Load sharing among trunked ports can be based on:

- Source and/or destination MAC address Port Mirroring
supports 2 mirroring ports in managed mode supports a dedicated mirroring port in unmanaged mode

Built-in MIB statistics counters Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Full set of LED signals provided by a serial interface Recognizes Simple Bandwidth Management (SBM) and Resource Reservation Protocol (RSVP) packets and forwards to CPU Built-in reset logic triggered by system malfunction Built-in self test (BIST) for internal and external SRAM

The is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps and a CPU interface for managed and unmanaged switch applications. The chip supports to 64K MAC addresses and to 255 tagged-based Virtual LANs (VLANs). The centralized shared memory architecture permits a very high performance packet forwarding rate at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. A Frame Buffer Memory domain utilizes cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously. With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50416 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50416 recognizes a total of 16 UDP/TCP logical ports, 8 hardwired and 8 programmable (including one programmable range). The ZL50416 supports 2 groups of port trunking/load sharing. Two groups are dedicated to 10/100 ports, where each 10/100 group can contain to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50416 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface creating a complete network management solution. The ZL50416 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The ZL50416 is packaged a 553-pin Ball Grid Array package.


 

Related products with the same datasheet
ZL50416/GKC
Some Part number from the same manufacture Zarlink Semiconductor
ZL50418 Managed 16-Port Fast Ethernet + 2-Port 1 Gb Ethernet switch The ZL50418 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 16 ports at 10/100 Mbps,
ZL30406 C-48 STM-16 SONET/SDH Clock Multiplier PLLThe ZL30406 is a SONET (synchronous optical network) and SDH (synchronous digital hierarchy) clock multiplier analog phase locked loop (APLL) providing six output
ZL30414 OC-192 STM-64 SONET/SDH Clock Multiplier PLL The ZL30414 is an analog phase-locked loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET
ZL50405 Managed 5-Port Fast Ethernet Switch The ZL50405 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 5 ports at 10/100 Mbps and a CPU interface for managed
ZL50409 Managed 9-Port Fast Ethernet SwitchThe ZL50409 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 9 ports at 10/100 Mbps and a CPU interface for managed
ZL50400 Lightly Managed/Unmanaged 9-Port Fast Ethernet Switch The ZL50400 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 9 ports at 10/100 Mbps and a CPU interface
ZL50404 Lightly Managed/Unmanaged 5-Port Fast Ethernet SwitchThe ZL50404 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 5 ports at 10/100 Mbps and a CPU interface
ZL50407 Lightly Managed/Unmanaged 8-Port Fast Ethernet + 1 Gb Ethernet SwitchThe ZL50407 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 8 ports at 10/100 Mbps,
ZL50411 Managed 9-Port Fast Ethernet Switch with Private VLANThe ZL50411 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 9 ports at 10/100 Mbps and a CPU interface
ZL50402 Managed 2-Port Fast Ethernet + 1 G Ethernet SwitchThe ZL50402 is a low density, low cost, high performance, non-blocking Ethernet switch. A single chip provides 2 ports at 10/100 Mbps, 1 port at 1 Gbps
ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer Product Status - Production File Download datasheetA full Design Manual is available to qualified customers. To register, please send an email
ZL30122 SONET/SDH Low Jitter Line Card SynchronizerThe ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable
ZL30123 SONET/SDH Low Jitter Line Card Synchronizer The ZL30123 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates
ZL38004 Dedicated Voice Processor with Dual Channel Codec The ZL38004 is supported by the ZLS38500 firmware pack for hands-free car kits and the ZLS38501 firmware pack for speakerphone.Features * 100 MHz (200
PX5410 he growing use of the Internet and the increasing demand for storage area network (SAN) solutions has created the need for next generation physical layer ICs. In addition the introduction of 4 G Fiber
PX5419A he Zarlink PX5419A 12X3 Gbps VCSEL Driver* with ACJTAG is a twelve-channel VCSEL driver designed for various 12x3 Gbps parallel PMD applications. It consists of a DC-coupled amplifier with selectable modulation
PX5420 The Zarlink PX5420 optical receiver is a single channel TIA/LA optical receiver designed for various applications to 4.25 Gbps. It consists of a transimpedance amplifier (TIA) and an AC-coupled differential
PX5514 The Zarlink PX5514 4x4 Gbps VCSEL Driver is a four-channel VCSEL driver designed for various 4x4 Gbps parallel optics and CWDM PMD applications. It consists of a DC-coupled amplifier with selectable modulation
PX5524 The growing use of the Internet has created increasingly higher demand for multi-Gbps I/O performance. The demand for 40+ Gbps WAN bandwidth fuels the growth of short-reach 10 Gbps infrastructures within
PX6410 The Zarlink PX6410 10 Gbps serial VCSEL driver is designed for various 10 Gbps PMD applications. It consists of a DC-coupled amplifier with adjustable modulation and bias currents optimized for driving
PX6419 The Zarlink PX6419 12X10 Gbps VCSEL Driver* is a 12-channel VCSEL driver designed for various 12x10 Gbps, 120 Gbps parallel optics and CWDM PMD applications. It consists of a DC-coupled amplifier with
 
0-C     D-L     M-R     S-Z