Details, datasheet, quote on part number: CZ80PIO
PartCZ80PIO
Category
DescriptionHereinafter Referred to As PIO, is a Dual-port Device
CompanyETC
DatasheetDownload CZ80PIO datasheet
  

 

Features, Applications

The CZ80PIO, hereinafter referred to as PIO, is a dual-port device which can be programmed by the system software to function as a broad range of peripheral devices that are compatible with the Z80CPU such as most keyboards, printers etc. System design is simplified because the PIO connects directly to the Z80CPU with no additional logic. In larger systems, address decoders and buffers may be required. The is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous, with no internal tri-states and a synchronous reset.

Features

Provides a direct interface between Z80 microprocessor systems and peripheral devices Two ports with interrupt-driven handshake for fast response Four programmable operating modes: Output Mode (both ports) Input Mode (both ports) Bi-directional (Port A only) Bit Control Mode (both ports) Programmable interrupts on peripheral status conditions

porta_i clk porta_o cdselect porta_tr portselect ce_n CZ80PIO m1_n iorq_n brdy rd_n bstb_n int_n ieo iei portb_i portb_ o

Applications

Programmable, dual - port device Interface for a wide range of peripheral devices such as: Keyboards Printers Paper table readers PROM programmers etc.

Name Type Description Clock clk In System Clock Interface to Processor Out Tristate controller for buffer for data bus data_i In Data bus input data_o Out Data bus output: rd_n In Read Cycle Status iorq_n In Input / Output Request ce_n In Chip Enable cdselect In Control / Data select portselect In Port / A select m1_n In Machine Cycle One Interrupt Service Routine int_n In Interrupt Request iei In Interrupt Enable Input ieo Out Interrupt Enable Output Control porta_tri In Tristate controller for buffer for data bus porta_i In Port B bus input porta_o Out Port B bus output portb_tri In Tristate controller for buffer for data bus portb_i In Port B bus input portb_o Out Port B bus output ardy Out Register A ready brdy Out Register B ready astb_n In Port A strobe pulse from peripheral device bstb_n In Port B strobe pulse from peripheral device data_tri

register specifies which of the eight data bits in the port are to be outputs and enables these bits; the remaining bits are inputs. The mask register specifies which of the bits in the port are masked.

The control logic consists of the CPU bus interface logic, interrupt control logic and internal control logic. The CPU bus interface logic interfaces the CZ80PIO directly to the so no external logic is necessary. For large systems, however, address decoders and/or buffers may be necessary. The interrupt control logic section handles all CPU interrupt protocol for nested-priority interrupt structures. Any device's physical location in a daisy-chain configuration determines its priority. Two lines (IEO and IEI) are provided in each PIO to form this daisy chain. The device closest to the CPU has the highest priority. Within a PIO, port A interrupts have higher priority then those of port B. In the byte input, byte output or bi-directional modes, an interrupt can be generated whenever the peripheral requests a new byte transfer. In the bit control mode, an interrupt can be generated when the peripheral status matches a programmed value.

The CZ80PIO megafunction is partitioned into modules as shown in figure 1 and described below.

Each port contains separate input and output registers, handshake control logic and the control registers. All data transfers between the peripheral unit and the CPU use the data input and output registers. The handshake logic associated with each port controls the data transfers through the input and the output registers. The mode control register (two bits) selects one of the four programmable operating modes. The Bit Control mode (mode 3) uses the remaining registers. The input/output control

clk cdselect portselect ce_n m1_n iorq_n rd_n int_n ieo iei
Flex Acex Apex Apex2 Cyclone Stratix Stratix-II
Notes: 1. Optimized for speed 2. Assumes all I/O is routed off-chip

 

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